Nonvolatile memories are widely used in various electronic systems, such as computer systems. There are various kinds of nonvolatile memories, such as read-only, programmable read-only, or floating-gate memories. A memory cell in a typical read-only memory (ROM) has an access transistor that is “programmed” during manufacture to be operable or inoperable in accordance with the desired data. A typical programmable read-only memory (PROM) cell has an access transistor and a polysilicon or metal fuse that is programmed by a user after manufacture but is programmable only once. A memory cell in a floating-gate memory, such as an electrically erasable read-only-memory (EEPROM), has a transistor with a programmable threshold voltage that allows a user to program the cell multiple times.
Generally and for purposes here, an unprogrammed memory cell stores a “0” and a programmed memory cell stores a logic “1.” For example, if the memory cell in a PROM is programmed, the fuse is “blown,” making the programmed memory cell nonconductive. Otherwise, the memory cell is conductive when enabled for reading the contents thereof.
Nonvolatile memories are generally arranged in an M word (M rows) by N bits per word (N columns) configuration, where N bits are typically read at a time (i.e., in parallel) from the memory. Each row of N memory cells is coupled to a corresponding one of M word lines, and each column of M memory cells is coupled to a corresponding one of N bit lines. During a read of the memory, an address decoder or the like coupled to the word lines enables one row of N memory cells and the contents of an enabled row of memory cells are sensed by N sense amplifier coupled to the N columns to produce an N-bit binary output from the memory. The sense amplifiers used in most nonvolatile applications are non-differential, e.g., each sense amplifier has a single input coupled to a corresponding bit line and a single output.
During a typical read cycle, each bit line is pre-charged to a fixed voltage (typically the voltage of the power supply for the memory), here a logic “1.” Then, an enabled memory cell storing a “0” at least partially discharges the corresponding bit line, while the memory cell storing a “1” does not significantly affect the bit line voltage. The resulting voltage level of the bit line is sensed by a sense amplifier, typically a simple CMOS inverter. The time it takes the voltage on the bit line to reach the switch point of the inverter defines the bit line access time and the number of memory cells and other circuit elements connected to a bit line influences the time it takes for a single memory cell to discharge the bit line. However, due to the leakage currents by the many memory cells connected to each of the bit lines, the bit line voltage may drift downward during a read, potentially causing a “0” to be read instead of a “1.”
To compensate for the leakage currents, anti-leakage “keeper” circuits are coupled to the bit lines to keep the bit lines near the pre-charge voltage during the read cycle. Due to manufacturing process variations and operating temperature conditions, the keeper circuits may be too strong relative to the capability of the memory cells or too weak to overcome the leakage currents: too strong a keeper might excessively extend the time required by a memory cell to discharge a bit line, causing a timing delay fault or even causing an incorrect output logic state fault; too weak a keeper could also cause an incorrect output logic state fault. These faults are most evident at process and temperature extremes. For example, operating at a high temperature a memory manufactured with a “slow” process (i.e., the transistors are “weak” relative to transistors made using a nominal process), the memory cell leakage currents might be so excessive so that one or more of the keeper circuits will not be sufficiently strong to keep the memory cell leakage current from pulling the bit line voltage too low during a read, resulting in “0” being read instead of a “1.” Conversely, when the temperature is low and the process “fast” (i.e., the transistors in the memory are “strong” relative to transistors made in a nominal process), the keeper circuits might be so strong that a memory cell storing a “0” will be unable to pull the bit line voltage low enough, resulting in a “1” being read instead of a “0.” Thus, there may only be a narrow temperature range and processing speed range for which the memory is operable. Moreover, since the leakage currents increases as the sizes of the transistors decrease and the total leakage current for each bit line is further aggravated as the number of memory cells coupled to each bit line increases, large memory designs implemented using very small geometries might not be practical to implement.